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   ǡXilinx FPGAʵý̳̣2棩һ̣ݰе2¡4¡6µ10ưļ
   ̸Ŀ¼7ļУļеݺͺ˵£
1.	chapt2ļеΪе2Ĺļ2ļУ
1	exp2_292-29Ӧļ
2	exp2_302-30Ӧļ
2.	chapt4ļеΪе4Ĺļ4ļУ
1	exp4_14-1Ӧļ
2	exp4_24-2Ӧļ
3	exp4_64-6Ӧļ
4	exp4_74-7Ӧļ
3.	chapt6ļеΪе6Ĺļ10ļУ
1	exp6_16-1Ӧļ
2	exp6_26-2Ӧļ
3	exp6_66-6Ӧļ
4	exp6_86-8Ӧļ
5	exp6_8_matlab6-8Ӧmatlabļ
6	exp6_96-9Ӧļ
7	exp6_126-12Ӧļ
8	exp6_136-13Ӧļ
9	exp6_186-18Ӧļ
10	exp6_UartUARTӿڿʵ
4.	chapt7ļеΪе7Ĺļ2ļУ
1	exp_sdk_C_code4ļУ
	led_cppLED룻
	uart_cppڴ룻
	intc_uartжϺʹϵĴ룻
	timer_intcʱжϵĴ롣
2	exp7_27-2Ӧļ
5.	chapt8ļеΪе8Ĺļ6ļУ
1	exp8_18-1Ӧļ
2	exp8_28-2Ӧļ
3	exp8_38-3Ӧļ
4	exp8_48-4Ӧļ
5	exp8_58-5Ӧļ
6	exp8_hwcosimӲЭӡ
6.	chapt9ļеΪе9Ĺļ5ļУ
1	exp9_19-1Ӧļ
2	exp9_29-2Ӧļ
3	exp9_39-3Ӧļ
4	exp9_49-4Ӧļ
5	exp9_59-5Ӧļ
7.	chapt10ļеΪе10Ĺļ1ļУ
1	exp10_110-1Ӧļ
2	xapp869Xilinx PCI-Eοĵ

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    ̵г»ͨ
   1Windows XP
   2Xilinx ISE Design Suite 13.2 for windows
    ϸϢԲο̲ʵ鲿ֵ˵
ע
   1ЩǰϸĶ̳ʵ鲿˵
   2ʵۺʵļԽʡռ䣬мɡ
   3ʹù̵ĳʱ뽫򿽱Ӳϣȥļֻԣ
   4Ҫ˵ǣڱصʱеĿ¼еһЩĿ¼·ʵ޸ġ
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    ʹô˹ʲô⣬ͨ·ʽϵ
   1ͨŵַ廪ѧ
        룺100084
        ϵˣʢ
        ʼshengdl@tup.tinghua.edu.cn
   2ͨŵַʵѧ101
        룺100876
        ϵˣĲ
        ʼxuwb@bupt.edu.cn
